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Minisymposium
MS3D - Riding the Cambrian Explosion in Hardware for Scientific Computing
Replay
Session Chair
Description
Scientific computing has relied upon commodity components for many years, and currently most popular are x86 CPUs and Nvidia GPUs. However, there is a Cambrian explosion of new types of hardware for accelerating scientific codes and as such a wealth of other options are becoming available. These include extremely high-core count CPUs (e.g. the CS-2 and GraphCore), highly vectorised and flexible processing elements (e.g. AMD’s AI engines, Google TPUs), Field Programmable Gate Arrays (FPGAs) and a range of technologies built upon RISC-V (e.g. the 1000 core Esperanto accelerator). Furthermore, many of these new architectures are capable of being highly energy efficient and-so potentially provide a route to delivering improved performance at reduced environmental cost. However, a major challenge is around how scientific application developers can leverage these technologies, and whether they actually deliver the benefits that the vendors claim. This minisymposium will bring together experts in developing these novel technologies and leveraging them for HPC application acceleration, with the scientific community. We will explore the potential benefits of these new architectures, which ones optimally suit what application properties, and discuss some of the challenges that must be overcome for them to become mainstream in scientific computing.
Presentations
The Cerebras CS2 is a wafer scale processor with 850,000 simple cores connected with a 2D mesh network. The CS2 has enjoyed tremendous success in the AI space both in performance and ease of use, allowing users to interact with it through a familiar framework - Pytorch. However, it is also possible to program the wafer directly using the Cerebras SDK using CSL, a proprietary domain specific language. This can be a daunting task where researchers have to learn a new language and hardware details, as well as a different way of designing algorithms in a data-flow manner. The architecture of the CS2 is well suited to linear algebra, an integral part to many scientific computation algorithms, so it would be beneficial to have an easier point of entry. To this end, we have been creating an interface to the linear algebra library PETSc and associated Cerebras SDK back-end code with the aim of lowering the barrier to entry to using the CS2 for scientific applications. In this talk we will describe our efforts in this project as well as the experience and lessons learned from using and programming the Cerebras wafer scale processor.
RISC-V is an open standard Instruction Set Architecture (ISA) enabling a new era of processor innovation through open collaboration. It brings new opportunities for researchers and industry to go further than any time before; and Barcelona Supercomputing Center (BSC-CNS) is a good example of that within the High-Performance-Computing domain. BSC-CNS is one of the most relevant European HPC research centers, which actively promotes the adoption, design and development of solutions based on RISC-V as an alternative to non-European vendors. Nowadays HPC is playing a key role in our modern world, not only for accelerating traditional complex applications, but also emerging ones. In addition, application domains for HPC are more diverse, and they are not limited to supercomputers. Day by day, HPC is more strategic for socioeconomical sectors such as industry 4.0 and/or automotive, just to mention some. In this direction, BSC is actively involved in multiple activities aiming to foster collaboration and paving the way for overcoming some of the current challenges that powerful workloads are facing. This talk shows a landscape of RISC-V initiatives at BSC, and how those might potentially impact and benefit HPC workloads and potentially how to use and program those to run in future supercomputers.
In this presentation, I will introduce the AMD University Program and the academic solutions available for the community. Then, I will introduce the AMD Ryzen AI which is the first in a new class of Neural Processing Units (NPU) designed for x86 computers. Built on the AMD XDNA™ spatial dataflow computer architecture, the NPU consists of a tiled array of AI Engine processors, a set of VLIW vector processors with adaptable interconnect, designed to offer lower latency and better energy efficiency. Finally, I will present a set of platforms enabled by the AMD XDNA™ and the software tools available.
This panel will explore the issues and aspects raised during the mini-symposium, cutting across the themes to explore overlap and divergences between the technologies and view points