Teresa Cervero got her PhD in Telecommunication Engineer by the Univ. of Las Palmas de Gran Canaria (Spain) in 2013 with a thesis focused on dynamic reconfiguration based on FPGAs for video and hyperspectral image processing. After that, she worked a few years as a consultant, and later explored the entrepreneurship path as part of a small tech start-up; period in which she moved from hardware to software Moving back to research, she joined Barcelona Supercomputing Center (BSC-CNS) in 2020 as Leading Research Engineer in Computer Science department. Her current research interests are focused on design and development of RISC-V based accelerators for HPC, and FPGA-based emulation and acceleration tools and systems. From the moment Teresa joined BSC till 2023 she played the role of hardware coordinator of the MareNostrum Experimental Exascale Platform (www.meep-project.eu) project, funded by EuroHPC JU. Currently she is leading the Laboratory for Open Computer Architecture (LOCA) initiatives with the aim of fostering inter-departmental and international collaboration at BSC, as part of the Severo Ochoa Programme. In addition to that, she is member of the Red-RISCV network (http://www.red-riscv.org/) and the Steering Committee of the RISC-V Summit Europe (https://riscv-europe.org/). She also contributes to HPC open hardware ecosystem by organizing events that put together professionals interested in the field to present new ideas, novelties on different layers of the stack, and products. These events also facilitate sharing knowledge, experience, and networking among the participants